On evaluating competing bridge fault models for CMOS ICs
نویسندگان
چکیده
We compare the accuracy, speed and applicability to test generation of existing bridge fault modeling solutions. We identify some previously undiscussed anomalous circuit behaviors, and describe the extent to which they a ect bridge fault simulation and testing. Finally, we present a system for evaluating bridge fault models in a test generation environment, and we present an experiment that provides an assessment of how defect coverage can be a ected by a generating and checking model.
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